1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising high-k metal gate electrode structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions representing an interface that is formed by highly doped regions, referred to as drain and source regions, and by a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the electronic characteristics of the channel regions, such as dopant concentration, band gap, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the base material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. It turns out that decreasing the channel length requires an increased capacitive coupling between the gate electrode and the channel region to avoid the so-called short channel behavior during transistor operation. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide based dielectrics, at least in part, as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would otherwise be obtained by an extremely thin silicon dioxide layer.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material at least in the vicinity of the gate dielectric material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals may be formed so as to connect to the high dielectric material, thereby substantially avoiding the presence of a depletion zone and providing superior conductivity compared to the doped polysilicon material. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration and the performance characteristics thereof has to be guaranteed when using metal-containing electrode materials.
In addition to providing sophisticated high-k metal gate electrode structures, other mechanisms are typically implemented in transistors in order to increase the overall performance, for instance, in terms of the electronic characteristics of the channel region. For example, it is well known that the charge carrier mobility in the channel region may be efficiently modified by inducing a strained state therein, which may be accomplished by various strain-inducing mechanisms, such as providing an embedded strained semiconductor material in the drain and source regions, thereby inducing a desired strain component in the channel region.
For example, silicon/germanium is frequently used in P-channel transistors in the drain and source areas in order to induce a compressive strain in the channel region of the P-channel transistor. The approach of providing an embedded strain-inducing semiconductor material, such as a silicon/germanium material, in the active regions of transistors is typically implemented by forming cavities in the active regions adjacent to the gate electrode structures and by providing the semiconductor alloy, such as the silicon/germanium alloy, by using selective epitaxial growth techniques, wherein the material composition and the offset of the semiconductor alloy substantially determine the finally obtained strain in the channel region of the transistor. Generally, the incorporation of a strain-inducing silicon/germanium alloy into the active region of the P-channel transistors is a very promising approach, which essentially contributes to a gain in performance of sophisticated transistors. In combination with sophisticated gate electrode structures, which comprise a high-k dielectric material in combination with a metal-containing electrode material, however, a significant gain in performance is no longer observed, which is assumed to be caused by the interaction of a threshold adjusting mechanism of the P-channel transistor with the strain-inducing semiconductor alloy in the drain and source areas. That is, typically in sophisticated approaches, the threshold voltage adjustment of complex high-k metal gate electrode structures may be accomplished in an early manufacturing stage, i.e., upon forming the gate electrode structures, which may require the incorporation of a specific channel semiconductor material at a surface of the active regions of one type of transistor in order to achieve a required offset of the band gaps between P-channel transistors and N-channel transistors, since providing work function adjusting metal species in the gate electrode structures of transistors of different conductivity type may not be sufficient. The additional channel semiconductor material is frequently provided in the form of a semiconductor alloy, such as a silicon/germanium alloy, wherein the thickness of the additional semiconductor material and the material composition may have a significant influence on the finally achieved threshold voltage of the transistor under consideration. For example, a silicon/germanium alloy is frequently used in P-channel transistors as a surface layer of the active regions on which the high-k metal gate electrode structure is formed, wherein, in combination with a specific configuration of the gate insulation layer and the subsequent metal-containing electrode material, the thickness of the surface layer and the composition thereof, i.e., the germanium concentration, determine the resulting transistor characteristics. It is believed, however, that the channel semiconductor alloy may increasingly interact with the strain-inducing semiconductor alloy provided in the drain and source areas, in particular when reduced transistor dimensions are to be implemented.
With reference to FIGS. 1a-1b, a typical process flow for forming transistors including sophisticated high-k metal gate electrode structures is described in order to identify the problems involved in this conventional process strategy.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage. As illustrated, the device 100 comprises a substrate 101, above which is formed a semiconductor layer 102 that, in turn, is divided into a plurality of active regions 102A, 102B by means of an isolation structure 102C. In the example shown, the active region 102A corresponds to a P-channel transistor 150A, while the active region 102B corresponds to an N-channel transistor 150B. It should be appreciated that, in this context, an active region is to be understood as a semiconductor region in and above which one or more transistor elements are to be formed. As discussed above, the active region 102A comprises a channel semiconductor material 103 in the form of a silicon/germanium alloy, i.e., in the form of a crystalline silicon/germanium mixture, wherein the layer 103 may represent a surface layer that in the manufacturing stage shown covers the entire active region 102A. Typically, a thickness of the layer 103 may be in the range of 8-50 nm, while a germanium concentration may be in the range of 25 to approximately 30 atomic percent. As discussed before, the material composition, i.e., the germanium concentration, and the thickness of the layer 103 may significantly influence the finally obtained threshold voltage of the transistor 150A. Moreover, the transistor 150A comprises a gate electrode structure 110A, while the transistor 150B comprises a gate electrode structure 110B. The gate electrode structures 110A, 110B represent sophisticated high-k metal gate electrode structures and thus comprise gate insulation layers 111A, 111B, respectively, and metal-containing electrode materials 112A, 112B, respectively. Moreover, an amorphous silicon material 113 is formed above the respective metal-containing electrode materials 112A, 112B, followed by a cap layer or layer system 114, for instance comprised of silicon nitride, silicon dioxide and the like. Furthermore, both gate electrode structures 110A, 110B may comprise a sidewall liner or spacer 115 in order to preserve integrity of the sensitive materials of the gate electrode structures, wherein typically silicon nitride and the like may be used. Furthermore, the gate electrode structure 110A comprises a sidewall spacer 116A, which may define the lateral offset of cavities 104 to be formed in the active region 102A. On the other hand, the gate electrode structure 110B is covered by a spacer layer 116 in order to protect the gate electrode structure 110B and the active region 102B during the further processing.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The isolation structure 102C may be formed on the basis of sophisticated lithography, etch, deposition and planarization techniques in order to implement the structure 102C in the form of a shallow trench isolation. Consequently, by forming the shallow trench isolation within the initial semiconductor layer 102, the active regions 102A, 102B are laterally delineated. After or prior to forming the isolation structure 102C, appropriate dopant species are incorporated into the active regions 102A, 102B by using well-established masking regimes and implantation techniques. Furthermore, a mask may be formed so as to cover the active region 102B in order to apply a selective epitaxial growth process for forming the surface layer 103 in the form of a silicon/germanium alloy. To this end, an appropriate dielectric material, such as silicon dioxide, is formed on or above the active regions 102A, 102B and is then selectively removed from the active region 102A. If desired, a certain recess may be formed in the active region 102A in order to provide a substantially planar surface topography after depositing the material of the layer 103, as for instance shown in FIG. 1a. To this end, any well-established etch techniques may be applied. Thereafter, the material of the layer 103 is deposited by using well-established selective epitaxial growth techniques in which process parameters, such as flow rates of precursor gases and the like, are appropriately selected such that a desired material composition is obtained and a material deposition is substantially restricted to exposed crystalline surface areas, while a significant material deposition on dielectric surface areas is suppressed. In order to provide an appropriate band gap offset in the upper portion of the active region 102A compared to the active region 102B, typically a high germanium concentration is desirable, wherein presently available deposition recipes may allow germanium concentrations of up to approximately 30 atomic percent. Consequently, upon depositing the layer 103, the mismatch in the natural lattice constants between the material of the layer 103 and the silicon material of the active region 102A may result in a certain degree of strain within the layer 103 and also in the material of the active region 102A in the vicinity of the layer 103.
After the deposition of the material 103, the mask formed above the active region 102B is removed and appropriate material layers are formed in order to provide the gate insulation layers 111A, 111B and the metal-containing electrode materials 112A, 112B. To this end, sophisticated process strategies are applied wherein, if required, a very thin conventional dielectric material, such as silicon oxynitride, may be formed, followed by the deposition of a high-k dielectric material such as a hafnium oxide-based material and the like. Moreover, electrode-containing materials may be deposited, for instance in the form of titanium nitride and the like, possibly in combination with additional work function adjusting metal species, such as aluminum, lanthanum and the like, wherein additional heat treatments may be performed so as to induce diffusion of any work function adjusting species and thermally stabilize the resulting material configuration. Consequently, after any such complex deposition and patterning regime, the gate insulation layers 111A, 111B and the electrode materials 112A, 112B are provided with desired electronic characteristics complying to the requirements of the transistors 150A, 150B, respectively. Thereafter, the amorphous silicon material 113 is deposited, thereby providing the material 113 with a substantially stress neutral behavior. Furthermore, the dielectric cap layer or layer system 114 is formed, possibly in combination with any additional sacrificial material, as required for patterning the resulting material layer stack. Thereafter, a complex lithography and etch sequence is applied in order to form the gate electrode structures 110A, 110B with the desired lateral dimensions, wherein a gate length may be 50 nm and less in sophisticated applications. It should be appreciated that the gate length is to be understood as the horizontal extension of the electrode materials 112A, 112B along the current flow direction, which is the horizontal direction in FIG. 1a. Next, the protective liner or spacer materials 115 are deposited, for instance by sophisticated low pressure chemical vapor deposition (CVD), multi-layer deposition techniques and the like, followed by a patterning of the layer in order to obtain the liners 115. Next, the spacer layer 116 is deposited and is locally anisotropically etched in order to form the spacer 116A, while the layer 116 is substantially preserved above the active region 102B. Thereafter, the cavities 104 are formed in the active region 102A, while using the layer 116 and possibly any resist material as an etch mask for the transistor 150B. The etch process for forming the cavities 104 may be performed on the basis of well-established plasma-based etch processes, wet chemical etch processes and the like.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a strain-inducing silicon/germanium alloy 105 is formed in the cavities 104 (FIG. 1a), which is accomplished by applying selective epitaxial growth techniques. As previously discussed, although a high germanium concentration may be desirable in view of increasing the mismatch of the natural lattice constants between the material 105 and the remaining material of the active region 102A, in presently available selective epitaxial growth techniques, the germanium concentration may not be arbitrarily increased. It rather appears that germanium concentrations above 25 percent are difficult to become realized when forming the embedded strain-inducing silicon/germanium alloy 105. Moreover, in many cases, it is advantageous to provide a varying germanium concentration, for instance a graded germanium concentration which may be advantageous for the further processing of the device 100, for instance in terms of forming metal silicide regions in the material 105, reducing the number of lattice defects upon forming the material 105 and the like. Consequently, frequently the material 105 may have a maximum germanium concentration that is less than the germanium concentration in the layer 103, which, however, is believed to cause a significant reduction of the efficiency of the strain-inducing mechanism of the material 105. Without intending to restrict the present application to the following explanation, it is believed that a significant strain component may exist in the layer 103 and thus also in the neighboring silicon area of the channel region 151, wherein, however, the strain component is inversely oriented compared to the strain component of the laterally adjacent silicon/germanium material 105. Consequently, a significant part of the strain obtained in the channel region 151 by means of the embedded material 105 may be compensated for or even over-compensated for by the strain induced by the material 103. On the other hand, a reduction of the germanium concentration in the layer 103, which would reduce the adverse effect on the overall strain conditions in the channel region 151, is less desirable since this would significantly influence the resulting threshold voltage of the transistor 150A. Similarly, a reduction of the thickness of the layer 103 would also result in a significant change of the finally obtained threshold voltage. Consequently, a change in one or both of these parameters of the layer 103 would require a complete redesign of the semiconductor device 100. On the other hand, an increase of the germanium concentration in the material 105 is difficult to achieve on the basis of currently available selective epitaxial deposition recipes.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.